1. Field of the Invention
The present invention related to a method and system for producing metal cored solder structures; and the present invention also relates to a metal cored solder decal structure for utilization in manufacturing semiconductor or flip chip interconnections.
2. Discussion of the Prior Art
The present state of the art is directed to increasing the Cu/Sn ratio in flip chip semiconductor interconnections in order to be able to exploit the benefits of the copper (Cu) content that is contained therein. Copper possess a high thermal conductivity of about 398 W/m·K and a low electrical resistivity of about 1.69 m·cm. In comparison, pure Sn has a thermal conductivity of about 67 W/m·K and an electrical resistivity of about 11.4 mΩ·cm, whereas eutectic PbSn solder has a thermal conductivity of about 51 W/m·K and an electrical resistivity of about 17.0 mΩcm. In the current state-of-the-art, there have been integrated Cu die-side bumps by using a Cu electroplating process in high-volume manufacturing quantities and with disclosed inherent reliability benefits that are related to stress, electromigration and thermal conductivity. Furthermore, it has been ascertained in the technology that the etched Cu post substrate technology can, potentially, reduce the actually expected thermal resistance of the semiconductor or flip chip interconnections.
Moreover, there is also described in Ference, et al., U.S. Pat. No. 5,244,143, that the C4 NP (controlled collapse chip connect new process) can be readily extended so as to be capable of providing high Cu/Sn ratio chip interconnections through the insertion of copper (Cu) spheres into the center of flip chip joints. U.S. Pat. No. 5,244,143 is commonly assigned to the present assignee, and the disclosure of which is incorporated herein by reference in its entirety. The foregoing concept is currently utilized as described in commonly assigned U.S. patent application Ser. No. 11/733,840, now U.S. Pat. No. 7,786,001, the disclosure of which is incorporated herein by reference in its entirety. In that instance, the application provides for an area array composite interconnect structure that is constituted of a copper core which is connected to respective bond pads on a semiconductor device, and a packaging substrate with a solder. However, pursuant to the foregoing co-pending patent application, a process of transferring is described as being implemented in two steps in a separate manner with the utilization of the solder and copper.
Moreover, pursuant to copending U.S. Ser. No. 11/733,840, the foregoing is limited to producing Cu cored solder bumps only on the surface of Si (silicon) wafer, whereas contrastingly in the technology there is currently a considerable need to provide for the formation of metal cored solder bumps on a substrate surface, inasmuch as the copper post that is prevalent on the substrate surface reduces the thermal resistance of the electrical interconnection.
In addition to the foregoing, other aspects known in the art are disclosed in Buchwalter et. Al., US Patent Publication Nos. 2009/0093111 and 2008/0251281; Gruber, U.S. Pat. No. 5,673,846, and Ference, U.S. Pat. No. 5,244,143; all of which are commonly assigned to the present assignee, and the disclosures of which are incorporated herein by reference in their entireties.
Flip-chip joints are shown in U.S. Pat. No. 7,786,001, commonly assigned to the present assignee, and which disclosure is expressly incorporated by reference herein in its entirety. U.S. Pat. No. 7,786,001 discloses an area array composite interconnect structure made up of a copper core connected to respective bond pads on a semiconductor device and a packaging substrate with solder. However, the method includes two steps of transfer processes of solder and Cu, separately. Also, U.S. Pat. No. 7,786,001 is limited to making Cu cored solder bumps only on the Si wafer side.
The known art uses a process utilizing copper Si die bumps by employing a copper electroplating process, and entails the need for an extremely expensive procedure, inasmuch as it necessitates the application of a lithographic process of thick photoresists, whereas other prior art publications disclose the use of copper post bumps on the side of the substrate, and which also require the implementing of lithographic processes for the etching of a copper layer.